1. Field of the Invention
This application relates to semiconductor processing technologies, and particularly to a method of annealing semiconductor substrates with rapid thermal processing.
2. Description of the Related Art
In today's high speed semiconductor devices, ultra-shallow junctions, low sheet resistance and abrupt lateral junctions are vital to reduce short channel effects and to increase transistor saturation current in source drain extensions. Several techniques have been developed to deal with the issues associated with the formation of shallow, low sheet resistance junctions. Examples of these issues are transient enhanced diffusion (TED), solid solubility, and channeling, which can be resolved by using low energy implants and sharp spike anneals. During low energy implant processes, the implant energies are limited to about 1 keV or less. Thus, TED is minimized because defects caused by the implant processes are confined close to the surface. Sharp spike anneals following the implant processes provide high dopant activation and effective implant damage removal while minimizing dopant diffusion.
Spike anneal is typically performed by subjecting a semiconductor substrate having implanted dopants to temperature treatment in a rapid thermal processing (RTP) system. A typical annealing profile using RTP involves ramping up to a target temperature, e.g. 1050° C., soaking the substrate at the target temperature for a period of time (soak time), and ramping down to a base temperature, e.g. 200° C. For spike anneal, high ramp rates, e.g., 75° C./sec or higher, and short (˜1 sec) or no soak time are desired to prevent excessive dopant diffusion. Besides the tight temperature control requirement, gas composition in the annealing ambient may also need to be controlled. For example, the presence of oxygen has been found to be necessary in order to decrease the evaporation or out-diffusion of implanted dopants such as boron and arsenic, but too much oxygen in the annealing ambient results in oxygen enhanced diffusion (OED) and limits the creation of shallow junctions, particularly when dopants such as boron are used.
Continued demand for smaller, more compact, faster, and more powerful chips forces the device geometries to scale down to and beyond the 100 nm node. Such aggressive downscaling in device geometries increase the Short Channel Effects (SCE). This reduces the differentiation between Ion (Idsat) (on state device current which is dependent on device type) and Ioff (off state device current or leakage currents), which reduction is essential for maintaining the device functionality. Thus the critical challenge in scaling device geometries is to maintain a distinction between Ion (Idsat) and Ioff.
A key to the challenge in scaling device geometries is in process/performance improvements in Ultra-Shallow Junction (USJ) technology. In a device, Ion (Idsat) depends on the amount of active dopant material within the device. Sheet resistance (Rs—as measured by a standard four-point probe method) is one way to measure activation. Higher activation typically provides lower sheet resistance. On the other hand, Ioff is dependent on the amount of dopant material that is diffused through the junction. Junction depth is measured as the depth in Angstroms (Å) at which the concentration of the measured species reaches a concentration of 1018 atoms/cm3, as measured by HRD (Dynamic) SIMS (Secondary Ion Mass Spectroscopy) profiles. As junction depth increases, Ioff increases. Thus, maintaining the differentiation between Ion and Ioff for USJ technology requires a smaller leakage (reduced junction depth) for the same or increased activation (reduced sheet resistance). The sheet resistance and junction depth (Xj) requirements for varying technology nodes are outlined in the International Technology Roadmap for Semiconductors (ITRS), 1999 & 2001 Edition, SIA, San Jose.
Current USJ technology involves ion implantation followed by a rapid thermal spike annealing process. The main parameters in any spike annealing process are the peak temperature (TP), and residence time (tR). A measure of spike sharpness, tR is defined as the time spent by the substrate within 50° C. of TP. Higher TP has the primary effect of causing increased activation, hence causing reduced RS and increased Ion. Different devices have different requirements of activation and hence different choices for TP. For the same TP, an increase in residence time has the primary effect of increasing diffusion, hence increasing the leakage currents. Thus, the main effort behind spike anneal is to reduce tR without compromising on the required level of activation.
Initial experiments on ramp up rates concluded that increasing ramp up rates greater than 180° C./second did not further improve the sheet resistance and junction depth profiles. Thus, there remains a need for reducing dopant diffusion during annealing of ultra shallow junctions while maintaining high dopant activation.